Reverse. Конфигурации

[vlad]

Но защелки и в самом деле могут работать непредсказуемо, сталкивался с этим.

Вот, не совсем как хотелось (отличия с первым примером явно видны). Получили мастер-помощник а, хотели к примеру просто защелку по (nCS = '0') AND (nIORIN = '0') с синхронным триггером...

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
--**********************************************************************************************
-- Input/Output Declarations
--**********************************************************************************************
ENTITY ReadSync IS
	PORT (
		RESET			: IN	std_logic;
		CLK			: IN	std_logic;
		nIORIN		: IN	std_logic;
		nCS			: IN	std_logic;
		ReadEnable	: OUT	std_logic
	);
END ReadSync;
--**********************************************************************************************
-- Architecture Body
--**********************************************************************************************
ARCHITECTURE rtl OF ReadSync IS
	SIGNAL SampledRead	: std_logic;
	SIGNAL SyncRead1		: std_logic;
	SIGNAL SyncRead2		: std_logic;
BEGIN
	--
	-- ReadSampleProc:	
	--
	ReadSampleProc: PROCESS ( nCS, nIORIN, CLK, RESET, SampledRead )
		VARIABLE next_SampledRead : std_logic;
	BEGIN
		IF ( RESET = '1' ) THEN
			next_SampledRead := '1';
		ELSIF ( (nCS = '0') AND (nIORIN = '0') ) THEN
			next_SampledRead := '0';
		ELSE
			next_SampledRead := '1';
		END IF;
		IF ( RESET = '1' ) THEN
			SampledRead <= '1';
		ELSIF ( CLK'EVENT AND (CLK = '1') ) THEN
			SampledRead <= next_SampledRead;
		END IF;
	END PROCESS ReadSampleProc;

	--
	-- ReadSyncProc:	The mode register synchronizer. Synchronizes
	--						changes in mode register data to the internal
	--						timing domain i.e. the falling edge of CLK.
	--
	ReadSyncProc : PROCESS ( CLK, RESET, SampledRead, SyncRead1, SyncRead2 )
		VARIABLE next_SyncRead1	: std_logic;	
		VARIABLE next_SyncRead2	: std_logic;

	BEGIN
		next_SyncRead1  := SampledRead;	
		next_SyncRead2  := SyncRead1;

		IF	( (SyncRead1 = '1') AND (SyncRead2 = '0') ) THEN
			ReadEnable <= '1'; 
		ELSE
			ReadEnable <= '0'; 
		END IF;

		IF ( RESET = '1' ) THEN         -- Asynchronous clear
			SyncRead1	<= '1';
			SyncRead2	<= '1';
    	ELSIF ( CLK'EVENT AND (CLK = '0') ) THEN
			SyncRead1	<= next_SyncRead1;
			SyncRead2	<= next_SyncRead2;
		END IF;

	END PROCESS ReadSyncProc;

END rtl;