MMC1 is unique in that not only the registers must be written to *one bit at a time*, but also you cannot write to the registers directly.
Internal registers are 5 bits wide. Meaning to complete a "full" write, games must write to a register 5 times (low bit first). This is usually accomplished with something like the following:
LDA value_to_write
STA $9FFF ; 1st bit written
LSR A
STA $9FFF ; 2nd bit written
LSR A
STA $9FFF ; 3rd bit written
LSR A
STA $9FFF ; 4th bit written
LSR A
STA $9FFF ; final 5th bit written -- full write is complete
Writing to anywhere in $8000-FFFF will do it, however the address you write to on the last of the 5 writes will determine which internal register gets filled. The address written to for the first 4 writes *does not matter at all*. Though games generally write to the same address anyway (like in the above example).
To illustrate this:
LDA #$00 ; we want to write 0 to a reg
STA $8000
STA $8000
STA $8000
STA $8000 ; first 4 writes go to $8000
STA $E000 ; 5th write goes to $E000
The above code will affects reg $E000 only!!! Despite $8000 being written to several times, reg $8000 remains totally unchanged!
How this works is that when the game writes to $8000-FFFF, it goes to a hidden temporary register. That register records the bits being written. Only after all 5 bits are written does the final 5-bit value move to the desired *actual* register.
Only bits 7 and 0 are significant when writing to a register:
Temporary reg port ($8000-FFFF):
[r... ...d]
r = reset flag
d = data bit
When 'r' is set:
- 'd' is ignored
- hidden temporary reg is reset (so that the next write is the "first" write)
- bits 2,3 of reg $8000 are set (16k PRG mode, $8000 swappable)
- other bits of $8000 (and other regs) are unchanged
When 'r' is clear:
- 'd' proceeds as the next bit written in the 5-bit sequence
- If this completes the 5-bit sequence:
- temporary reg is copied to actual internal reg (which reg depends on the last address written to)
- temporary reg is reset (so that next write is the "first" write)