На константы типа d800 - ругается.
Переделал так - растр пропал и сигнал не видит...
Код:
if ( pix_count < 800 ) pix_x <= pix_count; else pix_x <= 0;
if ( line_count < 600) pix_y <= line_count; else pix_y <= 0;
disp_enable <= ~((pix_count < 800) & (line_count < 600));
if(disp_enable)v_addr <= ((pix_y*800)+pix_x);
Весь код:
Код:
module vga_sync(
input clk_in, // Input 40 MHz clock, this is a pixel clock for this VGA mode
input reset, // Input async. active low reset signal
output reg vga_hsync, // Output horizontal sync signal
output reg vga_vsync, // Output vertical sync signal
output reg disp_enable, // Set when a writable portion of display is enabled:
output reg[9:0] pix_x, // x-coordinate of an active pixel
output reg[9:0] pix_y, // y-coordinate of an active pixel
output wire[7:0] data_out
);
//======================================================================
localparam SYNC_ON = 1'b1; // Define the polarity of sync pulses (psitive)
localparam SYNC_OFF = 1'b0;
localparam HSYNC_START = (840-1);
localparam HSYNC_END = (968-1);
localparam LINE_END = (1056-1);
localparam VSYNC_START = (601-1);
localparam VSYNC_END = (605-1);
localparam FRAME_END = (628-1);
localparam H_ACTIV = 800;
localparam V_ACTIV = 600;
reg [7:0] vram [0:4095]; initial $readmemh("vram.dat", vram);
reg[9:0] line_count; // Line counter, current line
reg[15:0] pix_count; // Pixel counter, current pixel
reg[19:0] v_addr; // vaddres counter
reg [1:0]SynRes;
always @( posedge clk_in )
begin
// reset
SynRes[1:0] <= {SynRes[0],reset};
// pixel count
if ( (SynRes[1] & ~SynRes[0]) | (pix_count == LINE_END) ) pix_count <= 0; else pix_count <= pix_count + 1;
// line count
if ( (SynRes[1] & ~SynRes[0]) | (line_count == FRAME_END ) ) line_count <= 0;
else if ( pix_count == LINE_END ) line_count <= line_count + 1;
// synhroimpulse
if (SynRes[1] & ~SynRes[0]) begin vga_hsync <=0; vga_vsync<=0; end
if(pix_count== HSYNC_START)vga_hsync <= SYNC_ON;else if (pix_count==HSYNC_END)vga_hsync<=SYNC_OFF;
if(line_count== VSYNC_START)vga_vsync <= SYNC_ON;else if (line_count==VSYNC_END)vga_vsync<=SYNC_OFF;
if (SynRes[1] & ~SynRes[0]) v_addr <=0;// or this: if (SynRes[1:0] == 2'b10)
else begin
if ( pix_count < 800 ) pix_x <= pix_count; else pix_x <= 0;
if ( line_count < 600) pix_y <= line_count; else pix_y <= 0;
disp_enable <= ~((pix_count < 800) & (line_count < 600));
if(disp_enable)v_addr <= ((pix_y*800)+pix_x);
end
end
assign data_out = vram[v_addr];
endmodule