module vga_sync(
input clk_in, // Input 25.175 MHz clock, this is a pixel clock for this VGA mode
input reset, // Input async. active low reset signal
output reg vga_hsync, // Output horizontal sync signal
output reg vga_vsync, // Output vertical sync signal
output reg disp_enable, // Set when a writable portion of display is enabled:
output reg[9:0] pix_x, // x-coordinate of an active pixel
output reg[9:0] pix_y, // y-coordinate of an active pixel
output reg[19:0] v_addr, // VRAM address count
output reg [7:0] data_out
);
//================================================== ====================
localparam SYNC_ON = 1'b0; // Define the polarity of sync pulses
localparam SYNC_OFF = 1'b1;
localparam HSYNC_START = 840-1;
localparam HSYNC_END = 968-1;
localparam LINE_END = 1056-1;
localparam VSYNC_START = 601-1;
localparam VSYNC_END = 605-1;
localparam FRAME_END = 628-1;
localparam integer H_ACTIV = 800;
localparam integer V_ACTIV = 600;
reg [7:0] vram [0:4095]; initial $readmemh("vram.txt", vram);
reg[9:0] line_count; // Line counter, current line
reg[15:0] pix_count; // Pixel counter, current pixel
reg[19:0] vaddr_count; // Pixel counter, current pixel
reg[7:9] temp_data;
always @( posedge clk_in or negedge reset )
begin
if (!reset) begin
line_count <= 0; // On a reset, restart counters from 0
pix_count <= 0;
vaddr_count<= 0;
v_addr =0;
end else begin
pix_count <= pix_count + 1'b1;// Increment a pixel counter every clock time!
vaddr_count <= vaddr_count + 1'b1;
if(vaddr_count==(V_ACTIV*H_ACTIV))
vaddr_count <=0;
// This is a state machine based on a pixel count. Since VGA modes timings are
// based on a multiple of pixel counts, we add them up and generate syncs at
// proper times
case (pix_count)
0: vga_hsync <= SYNC_OFF;
HSYNC_START: vga_hsync <= SYNC_ON;
HSYNC_END: vga_hsync <= SYNC_OFF;
LINE_END: begin
line_count <= line_count + 1'b1;
pix_count <= 0;
end
endcase
case (line_count)
0: vga_vsync <= SYNC_OFF;
VSYNC_START: vga_vsync <= SYNC_ON;
VSYNC_END: vga_vsync <= SYNC_OFF;
FRAME_END: line_count <= 0;
endcase
// The following code defines a drawable display region and outputs
// disp_enable to 1 when within that region. Also, set the pixel coordinates
// (normalized to the top-left edge of a drawable region)
disp_enable <= 0;
pix_x <= 0;
pix_y <= 0;
v_addr<=vaddr_count;
if (line_count>=0 && line_count<V_ACTIV)
begin
if (pix_count>=0 && pix_count<H_ACTIV)
begin
disp_enable <= 1;
pix_x <= pix_count;
pix_y <= line_count;
//data_out <=vram[vaddr_count];
end
end
end
end
always @( posedge clk_in)
begin
data_out <= vram[vaddr_count[11:0]];
end
endmodule
ZXM-Phoenix 1024+PROF ROM+SMUC+VGA
ATARI 800XL+SIO2PC+SIO2SD
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